A Robust Differential Logic Style with Nmos Logic Nets
نویسندگان
چکیده
In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.
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تاریخ انتشار 1997